Many micro-controllers have ports which allow programmers to move data on to and off of the chip. Typically, these ports are connected by a bus to the rest of the system as shown in FIG. 7. In the prior art system 100 of FIG. 7, the processor 112 is connected to fixed width (16 bit) ports by means of a bus which consists of two portions, a data bus 110 and an address bus 111. The address on the address bus 111 is decoded by one of the decoders 120 and enables an input or an output port. The addresses corresponding to these ports are fixed. Input data is received at one of the input/output (I/O) pads 180 and proceeds through a buffer 136 to an input register 128. Clocks 115 and other signals are input into a multiplexer 116 which supplies the input register 128. The clocks 115 and other signals received at the input register 128 can be selected from a variety of sources which can be internal or external to the micro-controller. An enable signal 140 from one of the decoders 120 enables the input data to pass through a tri-state buffer 124 and to be received at the data bus 110. Output data, being transferred from the data bus 110 to the I/O pads 180, first passes into one of the output latches 132. An output enable signal 141 from one of the decoders 120 enables the output data to pass from the latch 132 through a buffer 138 to the I/O pad 180. The output latches 132 and input registers 128 provide storage and can be substituted with other types of storage means, such as a FIFO register.
While the prior art system of FIG. 7 works well for data that is 16 bits wide, it is not very efficient for narrower data. For instance, if the micro-controller was reading data from a 10 bit wide CCD imaging device, then it would have to dedicate an entire 16 bit port to the input and, although only 10 pins are used, the other six pins of the port can not be used for any other purpose and are effectively lost. In FIG. 8, only the input ports of the prior art are shown, the output ports being essentially similar to the input ports except that an enabled latch may be used in place of a register, as in FIG. 7. In the prior art, all of the bits in a byte (8 bits) have the same clock signal and also the same fixed enable signal on to the bus. Therefore, there are at most two fixed enable signals and two clock selection mechanisms per port. In the port of FIG. 8, a first enable signal 143 and a first clock select signal 151 control the bits 0-7 of the data bus 110, while a second enable signal 144 and a second clock select signal 152 control the bits 8-15 of the data bus 110. In cases where there is only one fixed enable, the port has to be read from and written to as a 16 bit entity. Thus, in the prior art, unless the data is constructed in 8 bit or 16 bit entities, there will be extra unused pins in the port and the maximum capabilities of the port will not be fully utilized.
U.S. Pat. No. 4,758,746 to Birkner et al. provides a programmable logic array with individually programmable output pins to allow output terms to be routed via a programmable bus to selected pins. U.S. Pat. No. 5,872,463 to Pederson discloses a programmable logic device wherein each output bus conductor is connectable to one or more output drivers in order to make efficient use of the drivers that are provided. U.S. Pat. No. 5,804,985 to Shieh et al. discloses an output bus with 16 different output configurations for providing the proper signalling interface to peripheral devices. However, only one enable signal is provided to the device.
It is the object of the present invention to provide configuration circuitry to define virtual ports on a data bus that can be narrower than the physical ports so that narrower width data can be accepted by the virtual ports without causing the use of any data pins to be lost.
It is a further object of the invention to provide configuration circuitry that defines virtual ports that can span across two physical ports to allow greater flexibility in the use of the pins of the micro-controller.